SBIR Phase I: High performance non-volatile-memory circuits for artificial intelligence

Award ID: 2014959

The broader impact/commercial potential of this Small Business Innovation Research (SBIR) Phase I project is to enable wider adoption of Artificial Intelligence (AI) through development of a high-bandwidth, low-cost integrated circuit memory solution. AI is poised to make fundamental changes to how people live and work but require dramatic improvement in computing power and efficiency. So-called "edge AI" applications, such as smart home devices, smart city, and autonomous vehicles, will demand on-device AI subject to tight power and cost constraints. Current configurations with conventional memories may not offer a combination of performance, cost, power, operating temperature range necessary for many edge applications. The proposed project will advance the development of a new circuit architecture to address these challenges. This Small Business Innovation Research Phase I project develops high-speed analog circuit architectures and techniques in the context of emerging memory readout circuits. The proposed novel read circuit is applicable to magnetoresistive random-access memory (MRAM) and other emerging memories to achieve high performance and low power. This Phase I project will fully develop the concept and overcome key technical challenges that include (1) increasing differential amplifier speed and margin under severe area limitation, (2) reducing noise level and silicon area of a novel signal passing circuit, and (3) searching for an efficient way to serve typical data access requests with the novel read operation. The project goals are to validate the novel MRAM read circuit with silicon test data and perform a model study to quantify system level benefits. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

NSF Program Director: Ela Mirowski