SBIR Phase II: Logic compatible non-volatile neural network accelerator using analog compute-in-memory architecture

Award ID: 1951113

The broader impact/commercial potential of this Small Business Innovation Research (SBIR) Phase II project is to enable energy efficient smart internet of things (IoT) devices capable of running a neural network locally. The proposed energy-efficient neural network accelerator solution uses circuit architecture that allows for chips with a small area, a key enabler for cost-effective adoption and inclusion in space-constrained systems such as mobile devices. The solution is energy-efficient compared to the existing digital logic-based accelerator solutions, which will enable edge implementation for systems with power constraints. The manufacturing process is fully scalable in advanced standard logic processes at almost all manufacturing foundries, thus allowing for widespread adoption of the architecture. The outcome of this project will be an energy-efficient system on a chip (SoC) solution that offers artificial intelligence integration in smart IoT devices without cloud access, while enabling security and privacy enhancements. This Small Business Innovation Research (SBIR) Phase II project seeks to further develop an energy efficient analog circuit topology and variation tolerable system solution. To enable analog compute-in-memory architecture based neural network accelerator solution in an advanced semiconductor process technology, significant design challenges need to be solved with reduced supply voltage and noise margin. Along with the newly proposed area efficient and performance efficient analog compute-in-memory architecture solution, the logic compatible non-volatile neural network accelerator intellectual property core will be designed, fabricated, and validated in the advanced process technology through the project. Once verified successfully from the fabricated silicon in this project, the proposed neural network IP will be ready to be integrated as a key building block of future artificial intelligence systems on a chip and enable energy-efficient smart edge IoT devices. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

NSF Program Director: Benaiah Schrag